Multiple Abstraction Views of FPGA to Map Parallel Applications

Manipulating configurable resources like FPGAs in a codesign framework has become essential: especially, FPGAs may efficiently implement parallel systematic signal processing tasks. Nevertheless, such implementations are usually hand written at a low level. Our proposition is to provide high level modeling of an application and tools to automatically generate tuned VHDL code from these high level models. This paper introduces a flow able to fit a parallel application onto an FPGA according to the FPGA characteristics, and to map this application onto the FPGA. Each step of the flow requires specific details of the FPGA that realize the implementation. To get these details, several views of a same FPGA are introduced: BLACK BOX, QUANTITATIVE and PHYSICAL. The flow automatically generates the VHDL code of the initial application and a constraint file that guides the synthesis tools.